Job Descriptions

Sr. Digital Frontend Designer

Job Responsibilities

  • Front-End chip implementation including design, implementation and execution of the flow that starts with RTL code and ends with the delivery of a netlist package ready for physical design. 
  • Design documentation
  • Test plan generation

Job Requirements

  • MS degree of EE with minimum 3 years of work experience
  • Familiar with Verilog RTL design and Cadence design flow
  • Familiar with unix / linux and one or more scripting languanges (Perl, Python, tcl etc.)
  • Experience with UVM verification flow is preferred
  • Good communication skill
  • Experience with Ehternet Packet Parser/Classification design preferred

Sr. Analog / Mixed-Signal Design Engineer

Job Responsibilities

You will be working with a team of designers to design high performance RF/Analog/mixed-signal circuits for high-speed wireline transceiver products using state-of-the-art deep sub-micron CMOS technologies. 

  • Block level architecture design
  • Schematic design, simulation, behavioral modeling, validation plan
  • Supervise layout engineer and hands-on layout of critical paths when needed
  • Lab characterization

Job Requirements

  • MS or Ph.D in electrical engineering with minimum 2 years of experience
  • Solid understanding of circuit theory and signal processing principles
  • Experience designing a complete DSP-based communication system
  • Proficient in Cadence design environment
  • Good communication skills
  • Proficient in Python or other programming language preferred

Sr. Verification Engineer

Job Responsibility

  • Verification flow setup
  • Create regression flow using SQL database and job queue
  • Design verification

Qualification

  • BS or MS in EE / CS with minimum 5 years of experience
  • Familiar with Cadence design flow
  • Experience in using PLI routines
  • Strong in scripting language

Sr. Layout Engineer / Layout Manager

Job Responsibilities

  • Establish internal layout flow block level layout, chip integration to final tape out
  • Hands on layout of high speed high performance analog circuits
  • Manage in house layout engineers and external layout contractors

Job Requirements

  • BS degree in EE
  • 5 + years of layout design experience, 2+ years of FinFet experience
  • Understand ESD/Latchup, Power/GND, EM check, RF/analog design practices
  • Familiar with Cadence EDA tools
  • Prior experience in leading successful chip to production is desirable
  • Programming / scripting skills are desirable